THE NEXT FPGA PLATFORM

January 22, 2020
The Glasshouse
San Jose, CA

On January 22, 2020 we will be gathering some of the preeminent leaders in FPGAs on the application acceleration side for an extended day of discussions as part of The Next FPGA Platform event. The PowerPoint-free format, held in San Jose, CA., will feature live on-stage technical interviews and topical panels with FPGA technologist on the end user, developer, and creator sides, moderated by The Next Platform team and select guest interviewers.

 

WHAT TO EXPECT

The Next Platform has been tracking momentum with FPGAs over the last several years with particular emphasis on the role programmable devices will continue to play in application acceleration as well as in computational storage and modern datacenter networks.

In just the last five years there has been significant traction for FPGAs to accelerate a wide range of enterprise and research applications in areas as diverse as genomics, AI inference, large-scale business analytics, in-house EDA, and video transcoding, among others. At the same time there have been shifts in FPGA accessibility, device diversification, and performance/memory/efficiency improvements, along with many new twists along the path to more productive programming.

On January 22, 2020 we will be gathering some of the preeminent leaders in FPGAs on the application acceleration side for an extended day of discussions as part of The Next FPGA Platform event. The PowerPoint-free format, held in San Jose, CA., will feature live on-stage technical interviews and topical panels with FPGA technologist on the end user, developer, and creator sides, moderated by The Next Platform team and select guest interviewers.

There are countless questions to explore over the course of the event—and plenty of others for individual attendees to discuss at breaks and during the networking time that follows. Here are just a few. We welcome your thoughts on some you would like to see addressed as well.

  • One overarching theme will be focused on what is ahead for FPGAs in the datacenter. While the event will be primarily emphasizing application acceleration, we will discuss the concept of the FPGA-laden datacenter, with devices ranging from compute accelerators to where they fit in the network, storage, and at the edge. What does this mean for how future devices are designed?

  • To take that one step further, here’s the big question: when will FPGAs have a representative share, particularly in application acceleration? Remember when Intel bought Altera and made the bold claim that inference would soon be one-third of the cloud datacenter workload? Has that happened? And is scalable inference the key to future FPGA acceleration in the datacenter at scale? Or is the answer more nuanced? Think of it this way. The cost of bringing a server class chip to market is around a half billion dollars. It could be close to a billion over the next several years. At what point will ASICs stop making financial sense, opening the door to devices that do inference one moment and another workload the next on the same device? Will economics or workloads drive the future of FPGA penetration in the market?

  • Present and future (related to the above) we have FPGAs in client, edge, datacenter/application acceleration, inside SSDs/storage, and in the network. What is the distribution of these devices now and with all of these bulleted points in mind for the day, what will be in five years?

  • With that in mind, we want to survey the current state of FPGA accelerated applications. Where is the most traction and why? What is the overhead in the face of other options (GPU/CPU/ASICs) and what are the results? Challenges of deployment and benefits from programmability, cost over time, efficiency, suitability to broader workloads, etc. Examples from inference, transcoding, genomics, and other areas will be pulled into this discussion. And why is missing in key areas? For instance, why do we have yet to see an FPGA accelerated supercomputer? What happened industries like oil and gas? What is the momentum in financial services and how has that shifted over time?

  • We are entering into 2020 with a range of access options for FPGAs. From traditional on-prem to cloud-based instances, including the AWS F1 instances and those from Nimbix and smaller providers, what has traction been? What workloads are finding a home on the cloud? What about in-house FPGA development internally among cloud providers (Microsoft a good example here with Brainwave, among other projects), and how does this differ from what is happening with the biggest clouds in China? Are they deploying FPGAs in novel ways comparatively? Is there an appetite for FPGAs on cloud platforms worldwide? Why are cloud providers choosing to provide FPGAs in the first place? Where is the demand and what are the next steps to keep these efforts fed from users, vendors, and programmers?

  • What are some of the key technology innovations that will push capabilities of new devices? Here we will certainly discuss the role of high bandwidth memory as well as how key companies attempt to future proof the FPGA in terms of packaging technologies on the horizon and more broadly, in terms of whir ability to decrease latency in the datacenter. In other words, we will look at crucial hardware technology trends and what they mean for future devices and the users/programmers who will consume them. Finally on this note, we cannot completely avoid cost discussions. What are the brightest lights in FPGA application acceleration and how do technology creators follow those in 2020 and beyond?

  • And no forward-looking FPGA gathering could be complete without extensive discussions about programmability, developer enablement, tools, and frameworks. This is where the conversation risks going in several directions given the many discrete frameworks to operate within from both vendors and the open source community, which we believe will gain traction over the course of the next several years.

If you are reading these thoughts about where we are heading with The Next FPGA Platform and answering the questions to yourself or coming up with new ones, you’re in for a great day with us. This is the first time we’ve collected folks around FPGAs and we’re eager to see what happens conversationally throughout the day. It won’t be boring, to say the least.

Unlike traditional events that feature an unending stream of one-sided PowerPoint presentations, leaving attendees to form their own synthesis out of disparate bits, we will be starting at high-level points of synthesis and working backwards by letting the interviews break several questions down in the interview-based flow of the day. This format keeps marketing to a minimum while the day stays on track, focused, conversational, and unfolding more like a narrative on the state of FPGA acceleration rather than a choppy series of vendor slides without meaningful context.

The Next I/O Platform and The Next AI Platform, both of which focused on large-scale compute, storage, and network infrastructure both sold out rather quickly. Make sure you get registered as space is limited for this one-of-a-kind day that brings depth into the bigger picture and allows those present to help guide the conversation.

 
 

AGENDA FOR THE NEXT FPGA PLATFORM

January 22, 2020

8:30 - 9:00

REGISTRATION

Registration begins with coffee, light breakfast, and networking.

9:00 - 9:05

OPENING REMARKS

Introduction with hosts, co-founders and co-editors of The Next Platform, Timothy Prickett Morgan and Nicole Hemsoth.

9:05 - 9:35

MORNING KEYNOTE AND INTERVIEW: THE ROAD AHEAD FOR FPGAS IN THE DATACENTER

With Ivo Bolsens, CTO, Xilinx

9:35 - 9:55

FPGA DEVICE AND USE CASE EVOLUTION: THE BIG PICTURE.

Live interview with Dr. Paul Chow, University of Toronto.

9:55 - 10:15

CLOUD-BASED FPGA TRENDS, ADOPTION, AND FUTURE USE CASES.

One-on-one deep dive Steve Hebert, Nimbix.

10:15 – 10:35

BUILDING MOMENTUM FOR FPGAS: ARCHITECTURE AND POTENTIAL.

In-depth interview with Manoj Roge, Achronix.

10:35 – 10:50

NETWORKING BREAK

Coffee, tea, and light refreshments.

10:50 – 11:25

THE EVOLUTION OF FPGA USE AT MICROSOFT.

Extended interview and audience Q&A with Doug Berger, Microsoft.

11:25 – 11:40

THE FUTURE OF FPGAS IN HPC, LARGE-SCALE ANALYTICS.

With Dr. Antonino Tumeo, Pacific Northwest National Laboratory.

11:40 – 12:00

FPGA HARDWARE INNOVATIONS PANEL.

With Patrick Dorsey (Intel) Ivo Bolsens (Xilinx) and Manoj Roge (Achronix).

12:00 – 12:40

NETWORKING LUNCH

Enjoy a gourmet Glasshouse lunch and socialize with peers.

12:45 – 1:15

AFTERNOON KEYNOTE AND INTERVIEW: THE FUTURE OF RECONFIGURABLE DEVICES AND HETEROGENEOUS INTEGRATION 

Traditional keynote followed by one-on-one interview with Jose Alvarez, Intel.

1:15 – 1:35

THE KEYS TO FPGA ADOPTION AND ENABLEMENT

In-depth interview with Ramine Roane, Xilinx

1:35 – 1:55

FROM GLUE LOGIC TO THE BASIS OF AI, TRADING SYSTEMS. AN EVOLUTIONARY LOOK AT FPGA SOFTWARE/SYSTEMS.

Wide-ranging interview with FPGA veteran, John Lockwood.

1:55 – 2:10

TRENDS IN OPEN SOURCE FOR FPGA DEVELOPMENT.

With Naif Tarafdar, University of Toronto.

2:10 – 2:30

NETWORKING BREAK

Enjoy some downtime with peers. Coffee, tea, and light refreshments.

2:30 – 2:50

AUTOMATED DEPLOYMENT, SCALING, AND SHARING OF FPGA CLUSTERS

Live interview with Chris Kachris of InAccel.

2:50 – 3:15

THE EVOLUTION OF FPGAS FOR FINANCIAL SERVICES PLATFORMS: A SOFTWARE STORY.

With long-time Wall Street FPGA platform builder, Art Sedighi (now Microsoft).

3:15 – 3:35

FUTURE VISIONS FOR BOLSTERED FPGA PROGRAMMABILITY.

With Ofer Pravda of one of the original FPGA software companies, Gidel.

3:35 – 3:50

EMERGING REQUIREMENTS IN FPGA HARDWARE, SOFTWARE FOR SCALABLE USE CASES.

With Jeff Milrod, Bittware/Molex

3:50 – 4:10

NETWORKING BREAK

Socialize with peers and enjoy light refreshments and coffee/tea/

4:10 – 4:30

SOFTWARE INNOVATIONS AND ENABLEMENT PANEL

With Hua Xue (Intel), Chris Kachris (InAccel), Ramine Roane (Xilinx), Marcus Weddle, (Molex/Bittware)

4:30 – 4:50

FPGAS AS A PERVASIVE PRESENCE IN THE DATACENTER: A LOOK AT STORAGE/NETWORK OPPORTUNITIES.

How are storage and networking shaping the future of FPGAs throughout the datacenter? With Steven Bates (Eidetcom), Donna Yasay (Xilinx) Manish Muthal (Intel) and Scott Shadley (NGD Systems), John Bromhead (Titan-IC).

4:50 – 5:15

THE PAST, PRESENT AND FUTURE OF THE FPGA MARKET: INSIGHTS PANEL

With Lakecia Gunter (Intel), Kirk Saban (Xilinx), Reuven Weintraub (Gidel), and John Bromhead (Titan-IC) with opening analysis by Timothy Prickett Morgan.

5:15 – 5:20

CLOSING REMARKS FROM THE NEXT PLATFORM TEAM.

Analytical wrap-up of themes and topics from the day from Nicole Hemsoth and Timothy Prickett Morgan of The Next Platform.

HAPPY HOUR WITH THE NEXT PLATFORM 5:30 - 6:30

Round out the day with us on the patio. Enjoy cocktails and appetizers while we discuss the event and socialize.

 

OUR GUESTS INCLUDE...

NICOLE HEMSOTH (HOST/INTERVIEWER)

Nicole Hemsoth brings insight from the world of high performance computing following most recently a career covering supercomputing hardware and software as former Editor in Chief of long-standing supercomputing magazine, HPCwire. She was founding editor and conceptual creator of the data-intensive computing magazine Datanami, as well as the conceptual creator and founding Senior Editor for the large-scale infrastructure focused EnterpriseTech.

TIMOTHY PRICKETT MORGAN (HOST/INTERVIEWER)

Timothy Prickett Morgan brings 25 years of experience as a publisher, IT industry analyst, editor, and journalist for some of the world’s most widely-read high-tech and business publications including The Register, BusinessWeek, Midrange Computing, IT Jungle, Unigram, The Four Hundred, ComputerWire, Computer Business Review, Computer System News and IBM Systems User. Most recently, he was the Editor in Chief of EnterpriseTech.

IVO BOLSENS

Ivo Bolsens is senior vice president and chief technology officer (CTO), with responsibility for advanced technology development, Xilinx research laboratories (XRL) and Xilinx university program (XUP).

Bolsens came to Xilinx in June 2001 from the Belgium-based research center IMEC, where he was vice president of information and communication systems. His research included the development of knowledge-based verification for VLSI circuits, design of digital signal processing applications, and wireless communication terminals. He also headed the research on design technology for high-level synthesis of DSP hardware, HW/SW co-design and system-on-chip design.

DOUG BURGER

Doug Burger is one of the world’s leading active researchers in computer architecture, with a broad set of important contributions to his credit with extensive FPGA development at Microsoft. After receiving his PhD from University of Wisconsin in 1998, he joined UT Austin as a professor, receiving tenure in 2004 and becoming a full professor in 2008. His work on Explicit Data Graph Computing (EDGE) represents the fourth major class of instruction-set architectures (after CISC, RISC, and VLIW). At U. Texas, he co-led the project that conceived and built the TRIPS processor, an ambitious multicore ASIC and working EDGE system, which remains one of the most complex microprocessor prototypes ever built in academia. A number of Doug’s research contributions, such as non-uniform cache architectures (NUCA caches), are now shipping in Intel, ARM, and IBM microprocessors. He has been recognized as an IEEE Fellow and ACM Fellow.

PAUL CHOW

Paul Chow is a professor in the faculty of The Edward S. Rogers Sr. Department of Electrical and Computer Engineering at the University of Toronto where he holds the Dusan and Anne Miklas Chair in Engineering Design.  He was a major contributor to the early RISC processor technology developed at Stanford University that helped spawn the rapid rise of computing performance in the past 30 years.  Paul helped to establish the FPGA research group at UofT and did some of the early research in FPGA architectures, applications and reconfigurable computing.  He has two papers of the 25 papers selected as the most influential papers in the first 20 years of FCCM, the premier conference on reconfigurable computing.  His current research focuses on reconfigurable computing with an emphasis on programming models, middleware to support programming and portability, and scaling to large-scale, distributed FPGA deployments.

Paul has been the technical program and general chairs for FPGA, the premier conference on FPGAs, and for FCCM.  He co-founded AcceLight Networks to build a high-capacity, carrier-grade, optical switching system and is also a co-founder of ArchES Computing Systems, which is developing reconfigurable computing technology for the data centre.  Paul is on the Board of Directors of CMC Microsystems and chairs the CMC Advisory Committee.

JOHN LOCKWOOD

A pioneer in FPGA accelerated applications and beyond, Lockwood has founded three companies in the areas of low latency networking, Internet security, and electronic commerce and serves as CEO of Algo-Logic Systems, Inc. 


He has worked at the National Center for Supercomputing Applications (NCSA), AT&T Bell Laboratories, IBM, and Science Applications International Corp (SAIC). As a professor at Stanford University, he managed the NetFPGA program from 2007 to 2009 and grew the Beta program 10 to 1,021 cards deployed worldwide. As a tenured professor, he created and led the Reconfigurable Network Group within the Applied Research Laboratory at Washington University in St. Louis. He has published over 100 papers and patents on topics related to networking with FPGAs and served as served as principal investigator on dozens of federal and corporate grants. He holds BS, MS, PhD degrees in Electrical and Computer Engineering from the University of Illinois at Urbana/Champaign and is a member of IEEE, ACM, and Tau Beta Pi.

ART SEDIGHI

Dr. Sedighi is a Wall Street Technology Executive with over 20 years of experience planning, designing, developing and having end-to-end ownership of large enterprise-wide solutions in fintech.

He was the founder and CTO of a dense-computing systems company, acquired by Univa in 2008. Art became the Global Head of HPC and Grid Engineering at Bank of America/Merrill Lynch then moved to Morgan Stanley, focusing on design and implementation of the Target State Architecture (TSA) . He then joined Noble Markets as the VP of engineering, where he ran product development/engineering for an FX real-time clearing infrastructure.  He has designed and implemented trading and exchange platforms for the New York Stock Exchange, NASDAQ and the American Stock Exchange. Dr. Sedighi received his PhD from Texas Tech University in Systems Engineering, holds a Masters in Bioinformatics from the Johns Hopkins University, and a Masters in Computer Science from Rensselaer Polytechnic Institute.

STEPHEN BATES

Stephen Bates is the CTO of Eideticom and is a renowned expert on topics like Computational Storage, Persistent Memory, NVMe, RDMA, TCP/IP and FPGAs. He has worked on a range of complex storage and communication systems including NVMe controllers and PCIe switches developed by his former employer Microsemi (formerly PMC-Sierra). He enjoys working at the interface between hardware and software and is an active contributor to the Linux kernel. Before Eideticom he worked in the CTO office at PMC-Sierra and before that he was an Assistant Professor in Computer Engineering at The University of Alberta. He holds a PhD degree from The University of Edinburgh, Scotland.

STEVE HEBERT

Steve Hebert is CEO and co-founder of Nimbix, which began with the goal of expanding the reach of FPGAs. He got his start in semiconductors with Texas Instruments after earning his degree in Electrical Engineering from Santa Clara University. Today, he is a technology industry veteran of over 20 years with a strong track record of operational execution and sales growth at both startup and large companies. Prior to Nimbix, he led a global sales team in the computing segment with programmable chip-maker, Altera. An entrepreneur, builder and inventor at heart, Steve’s vision is aimed at solving the world’s biggest challenges with supercomputing.

MANOJ ROGE

Manoj Roge is VP of Strategic Product Planning at Achronix. He has over 23 years of semiconductor and systems experience. Previously, Manoj has held senior management positions at Xilinx, Intel-PSG and Cypress Semiconductor. He successfully defined and executed new product strategies that resulted in significant increase in market share for the respective companies during his tenure. He has deep understanding of design requirements for broad set of market segments and fosters relationships with customers, ecosystem partners and standards bodies to deliver innovative solutions to market. He holds an MBA from Santa Clara University, MSEE from University of Texas, Arlington and BSEE from University of Mumbai. He holds 10 patents.

PUSHPDEEP ("PD") RAJPUT

Pushpdeep Rajput (PD) is among the leaders of FPGA strategy at Intel, focusing on partnerships and operations. Among his focus areas are the rich ecosystems of ISV and SI partnerships in the FPGA space as well as key alliances with open source ecosystem development, broader software development strategy and execution, and engagement with key accounts in cloud, database, and other application areas. PD received his MS, Electrical Engineering from North Carolina State University and his MBA in Marketing, Data Science and Strategy, and Corporate Strategy from the University of California, Berkeley, Haas School of Business.  

RAMINE ROANE

Ramine Roane is vice president of software and AI at Xilinx. Roane was instrumental in the introduction of the Vivado Design Suite in 2012, a modern electronic design automation (EDA) tool that helped give Xilinx a solid software foundation for hardware programmability. Prior to joining Xilinx in 2010, Roane held roles in management and software architecture in large software companies, as well as FPGA start-ups. He holds a Masters in Electronic Engineering and Computer Science from the National Polytechnic Institute of Grenoble (INPG), France.

NAIF TARAFDAR

Naif Tarafdar is a PhD candidate in the University of Toronto.  He is the chief architect of the Galapagos project, a large-scale project responsible for the deployment of distributed applications onto a cluster of heterogeneous devices. He has been interested in the applications of large scale heterogeneous applications for many years as the Galapagos project started with his course project for a course within his masters. His expertise ranges in different layers of the stack from creating infrastructure, device abstraction and networking and creating large clusters of devices. He also has had experience on the application side as an intern at Xilinx Research where he has worked on creating Machine Learning applications. During his tenure as a graduate student he has published his work in several top tier conferences within the FPGA community such as FPGA, FPL and FCCM, along with a chapter in the Springer Book: Hardware Accelerators in Data Centers. Naif strongly believes in pushing open-source projects within the hardware community, hoping to bring the community involvement and collaboration we see in the software community within hardware

ANTONIO TUMEO

Dr. Antonino Tumeo received the M.S degree in Informatic Engineering, in 2005, and the Ph.D degree in Computer Engineering, in 2009, from Politecnico di Milano in Italy. Since February 2011, he has been a research scientist in the PNNL's High Performance Computing group. He Joined PNNL in 2009 as a post doctoral research associate. Previously, he was a post doctoral researcher at Politecnico di Milano. His research interests are modeling and simulation of high performance architectures, hardware-software codesign, FPGA prototyping and GPGPU computing.

LAKECIA GUNTER

Lakecia Gunter is VP of Ecosystems Development and Operations in Intel’s Programmable Solutions Group. Prior to her current position, Lakecia was the Validation, Emulation, and FIVR manager in the Platform Validation Engineering organization of the Intel Architecture group, where she was responsible for delivering Intel’s 4th Generation Core Processor, Haswell, to the marketplace. She joined Intel in 2008 as technical program manager for the Café RIT Generation tools team in the Platform Validation Engineering organization and became the manager of the team in 2009. Lakecia earned a Master of Science in Electrical Engineering from Georgia Institute of Technology and a Bachelor of Science degree in Computer Engineering from University of South Florida. Lakecia also earned her Project Management Professional (PMP) Certification.

PREMAL BUCH

Dr. Premal Buch is Vice President in the Programmable Solutions Group and General Manager of Custom FPGA Engineering at Intel Corporation. He is responsible for the architecture and implementation of Intel's FPGA chips.
Prior to Robin.io where he served as CEO, Buch was the Vice President of Software Engineering at Altera, responsible for all its FPGA design tools. Under his tenure, Altera overhauled its Quartus-II tool suite, leading to the first release of Quartus Prime Pro and Fast Forward Compile, the first OpenCL compiler in the industry for FPGA based hardware acceleration and Altera’s first ARM-based embedded developer tool suite. Buch holds a bachelor's degree in electrical and electronics engineering from BITS Pilani and a masters and Ph.D. in electrical engineering and computer sciences from the University of California, Berkeley.

CHRIS KACHRIS

Christoforos Kachris is the founder and CEO of InAccel technologies that develop hardware IP cores for the acceleration of machine learning applications over Spark and other frameworks. InAccel provides modules for Amazon EC f1 platform that allows the speedup of Spark applications. His main expertise in on hardware acceleration of applications like network processing, image processing, high performance and cloud computing. he is the Technical Project Manager of the H2020 VINEYARD project working on efficient utilization of reconfigurable accelerator-based servers in the data centers

KIRK SABAN

Kirk Saban is the Vice President of Product and Technical Marketing at FPGA maker, Xilinx. He is responsible for Product and Technical Marketing of all Xilinx FPGAs, SoCs, MPSoCs, RFSoCs, ACAPs, Alveo Accelerator Cards, and evaluation boards. Responsibilities also include global customer training , sales training, sales enablement and corporate briefing center. He has held previous positions at Insight Electronics and RTDS Technologies.

MORE FEATURED GUESTS ADDED THIS WEEK...

Keep checking back as the agenda continues to evolve.

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